https://www.phoronix.com/scan.php?page=news_item&px=Ryzen-Compiler-Issues
It originally looked as an bug on GCC, but last research seems to confirm this is part of the older SMT/uop bug. Remember that earlier engineering samples had uop or the SMT disabled due to this bug. It seems that the bug wasn't completely corrected in retail chips. The problem seems to be traced down to the IRETQ instruction and it is not reproducible when threads are running on different cores.
AMD is recommending to disable SMT
https://community.amd.com/thread/216084
https://community.amd.com/message/2796982
Surely a microcode update will fix this.
It originally looked as an bug on GCC, but last research seems to confirm this is part of the older SMT/uop bug. Remember that earlier engineering samples had uop or the SMT disabled due to this bug. It seems that the bug wasn't completely corrected in retail chips. The problem seems to be traced down to the IRETQ instruction and it is not reproducible when threads are running on different cores.
AMD is recommending to disable SMT
https://community.amd.com/thread/216084
https://community.amd.com/message/2796982
Surely a microcode update will fix this.