SK Hynix Reveals Plans For Cutting-Edge HBM4E Memory, Development Expected By 2026

erek

erek

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“This is the first time we have the mentioning of the HBM4E, which not only validates the existence of the standard, but SK hynix has revealed subtle details about the process as well. HBM4E's feature bandwidth is reported to be 1.4 times higher than that of the previous generation, in this case, HBM4. It will be much more power efficient, which only shows us a glimpse of what to expect with next-gen AI accelerators.

Developments surrounding HBM4 surfaced a while ago when the Korean giant disclosed that it would utilize the MR-MUF development technique. This technique aims to integrate logic and memory semiconductors into a single package, and the firm has already formed an alliance with TSMC to reach this goal. Industry reports say that HBM4 will be the "iPhone moment" of the segment, establishing new benchmarks for later standards to follow.”

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Source: https://wccftech.com/sk-hynix-revea...ge-hbm4e-memory-development-expected-by-2026/
 
This gives me vibes of the Synergistic Processing Elements (SPE) from the PS3's cell processor? Just bigger?
 
I love that SKHynix named their new tech MR-MUF…

A little bit on how it works and how TSMC plays into it.
https://www.semianalysis.com/p/ai-expansion-supply-chain-analysis#§veeco-phased-out-sk-hynixs-hbm-packaging-innovation

https://www.semianalysis.com/p/intel-genai-for-yield-tsmc-cfet-and

The TLDR;
SK Hynix paired with TSMC to license their CoWoS packaging tech which they tweaked and built a more applicable bonding process that lets their HBM run cooler with less interference between the layers.
Lower temps with higher clocks, can better hold the performance peaks.

Samsungs memory isn’t “Defective” but it doesn’t compete.
 
DukenukemX said:
Surprised nobody is talking about how you can now replace LPDDR memory. It's called LPCAMM2.

View: https://youtu.be/K3zB9EFntmA?si=X3Twp3z0gGc-1s5O
Click to expand...

LPCAMM2 was first announced at CES this year, there aren't many devices using it yet.
I'm hoping it does become a thing because the more devices that use it the cheaper they get, which drives more devices to use it.
But it is way more cost-effective currently for OEMs to solder the memory, the CAMM format adoption has been pretty slow as a whole since DELL launched it.
But currently, you can't buy those modules from anybody.
 
Lakados said:
LPCAMM2 was first announced at CES this year, there aren't many devices using it yet.
I'm hoping it does become a thing because the more devices that use it the cheaper they get, which drives more devices to use it.
But it is way more cost-effective currently for OEMs to solder the memory, the CAMM format adoption has been pretty slow as a whole since DELL launched it.
But currently, you can't buy those modules from anybody.
Click to expand...
I'm guessing manufactures want you to pay the price they determine for memory, including having pricing tiers based on memory, similar to phones. Plus having forced obsolescence is a great motivator for future sales.

Hell I have a dirt cheap laptop with a really old cpu, But having the ability to swap out memory from 4gb to 16gb, and swap that hdd out for a sata ssd has made it quite usable again. It's still slower than a modern laptop, but I no longer am able to measure boot speed with a sundial either
 
sfsuphysics said:
I'm guessing manufactures want you to pay the price they determine for memory, including having pricing tiers based on memory, similar to phones. Plus having forced obsolescence is a great motivator for future sales.

Hell I have a dirt cheap laptop with a really old cpu, But having the ability to swap out memory from 4gb to 16gb, and swap that hdd out for a sata ssd has made it quite usable again. It's still slower than a modern laptop, but I no longer am able to measure boot speed with a sundial either
Click to expand...
Sort of, but yes. There are also two different non-compatible CAMM formats making the rounds and OEMs are torn between them and the iEEE is staying out of it.
Until there is just one, I doubt any 3'rd parties are going to bother with it unless it suddenly gets stupid popular.
 
Lakados said:
Sort of, but yes. There are also two different non-compatible CAMM formats making the rounds and OEMs are torn between them and the iEEE is staying out of it.
Until there is just one, I doubt any 3'rd parties are going to bother with it unless it suddenly gets stupid popular.
Click to expand...

TSMC Unveils Next-Generation HBM4 Base Dies, Built on 12 nm and 5 nm Nodes​

by AleksandarK Today, 04:48 Discuss (9 Comments)
During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.
 
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